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#1 nonggiatu

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Gửi lúc 13 Apr 2008 - 04:33 AM

Lên mạng google một cái không ngờ lại kiếm được cái này hay phết, mỗi tội là English, ai có time thì dịch ra đi, tớ lười lắm.
Xem đầy đủ tại đây:
http://www.ee.oulu.f...415A/exercises/

Còn đây là phần bài tập về CPU và Memory dành cho ai lười mò mẫm vào link trên:

PROBLEM 3.1(5-1)

A computer uses a memory unit with 256K words of 32 bits each. A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit, an operation code, a register code part to specify one of 64 registers, and an address part.

a) How many bits are there in the operation code, the register code part, and the address part?

b) Draw the instruction word format and indicate the number of bits in each part.

c) How many bits are there in the data and address inputs of the memory.
Memory
0 32 bits
1
...
256K 32 bits

Instruction word format
I OP-code Register Address
----------------------------------------------------------------------------------
Solution:

a)
Indirect 1 bit
Address 28 (256kB) * 210 (1024 bytes/kB) = 218 ==> 18 bits
Reg 64 registers = 26 => 6 bits
OP-code 32 - 1 - 18 - 6 bits = 7 bits

b)
I 31 OP 24-30 Reg 18-23 Address 0-17

c)

Address inputs: 18 (256K words)

data inputs: 32 (32 bits / word / memory reference)


PROBLEM 3.2(5-2)

What is the difference between a direct and an indirect address instruction? How many references to memory are needed for each type of instruction to bring an operand into a processsor register?

------------------------------------------------------------------------------------
Solution:

Direct:

One memory reference: Get the operand from the given address

Indirect:

Two memory references: Get the address of the operand from the given address and use this new address to get the value of the operand


PROBLEM 3.3(5-3)

The following control inputs are active in the bus system shown in Fig. 5-4. For each case, specify the register transfer that will be executed during the next clock transition.

See figure 5-21 for a functionality description of the Adder.
S2 S1 S0 value S LD(x) Memory Adder
a) 1 1 1 =7 IR READ -
b) 1 1 0 =6 PC - -
c) 1 0 0 =4 DR WRITE -
d) 0 0 0 =0 AC - ADD

----------------------------------------------------------------------------------------------

Solution:

See Fig. 5-4

a)
BUS(7) => Connect memory to the BUS
READ => Read from memory
LD(IR) => Load from bus to IR
Result : IR <- M[AR]

b)
BUS(6) => Connect register TR to the BUS
LD(PC) => Load from bus to PC
Result : PC <- TR

c)
BUS(4) => Connect register AC to the BUS
WRITE => Write to the memory
LD(DR) => Load from bus to DR
Result : M[AR] <- AC, DR <- AC

d)
BUS(0) => No effect
ADD => Add DR to AC
Result : AC <- AC + DR


PROBLEM 3.6(5-6)

Consider the instruction formats of the basic computer shown in Fig. 5-5 and the list of instructions given in Table 5-2. For each of the following 16-bit instructions, give the equivalent four-digit hexadecimal code and explain in your own words what it is that the instruction is going to perform.

a) 0001 0000 0010 0100

b) 1011 0001 0010 0100

c) 0111 0000 0010 0000

-------------------------------------------------------------------------------------

Solution:

a)
Instruction 0001 0000 0010 0100
Hex. 1 0 2 4

=> direct ADD:

AC <- M[AR] + AC ; Address = 24

b)
Instruction 1011 0001 0010 0100
Hex. B 1 2 4

=> indirect STA:

AR<-M[AR]

M[AR] <- AC ; Address is found at address 124

c)
Instruction 0111 0000 0010 0000
Hex. 7 0 2 0

=> INC:

AC <- AC + 1




PROBLEM 3.7(5-9)


The content of AC in the basic computer is hexadecimal A937 and the initial value of E is 1. Determine the contents of AC, E, PC, AR and IR in hexadecimal after the execution of the CLA instruction. The initial value of PC is hexadecimal 021.

Initial conditions:

AC = A937h
E = 1
PC = 021h

See figure 5-6 for hints

-------------------------------------------------------------------------------------------

Solution:

Execute CLA (Instruction code 7800h)

Fetch:
AR <- PC ; => (AR) = (PC) = 021h
IR <- M[AR] , PC <- PC + 1 ; => (IR)=7800h, (PC) = 022h

Decode:
D0,...,D7 <- decode IR(12-14)
AR <- IR(0-11), I <- IR(15) ; =>(AR) = 800h (12 address bits)

Execute:
AC <- 0 ; (AC) = 0
Summary:
(AC) = 0h, (AR) = 800h, (PC) = 022h, (IR) = 7800h, E= 1




PROBLEM 3.8(5-7)

A basic computer is starting to perform instruction ADD 100 I. Given preconditions are (values are hex decimals):

* PC = 190
* AC = 3
* M[100] = 200
* M[200] = fffe

a) Describe what happens during the instruction cycle. Include all phases from fetch to execute.

b) If an I/O device requests for an interrupt during the instruction cycle, what happens? Describe the events starting from the fetch phase of the current instruction until the machine is ready to branch to the interrupt subroutine of the I/O device.

See figure 5-15.

--------------------------------------------------------------------------------

Solution:

a)

Before fetch, we branch to the instruction cycle (R = 0).

Fetch:
R'T0: AR <- PC ; AR = PC = 190
R'T1: IR <- M[AR] , PC <- PC + 1 ; IR = 9100, PC = 191

Decode:
R'T2: D0,...,D7 <- decode IR(12-14) ; D1 = 1
AR <- IR(0-11), I <- IR(15) ; I = 1, AR = 100

Determine whether instruction is memory reference, register or I/O. Because D1 was set to 1, all other decoder outputs Dn are set to 0 (see figure 5-6). Therefore the instruction is a memory-reference instruction.

Indirect:
D7'IT3: AR <- M[AR] ; AR = 200

Execute:
D1T4: DR <- M[AR] ; DR = fffe
D1T5: AC <- AC + DR, ; AC = 1
E <- C(out), SC <- 0 ; E = 1

Remember that SC (Sequence Counter) is incremented on every clock pulse Tn.

b)

Because we are already in the instruction cycle, the current instruction is performed as in a). After the execution of the instruction is completed, the computer branches to interrupt cycle (R = 1). R is the interrupt request signal.

First in the interrupt cycle, the return address of the current program is saved to memory location 0.

RT0: AR <- 0, TR <- PC
RT1: M[AR] <- TR, PC <- 0 ; M[0] = 191

The interrupts are disabled and the program flow continues at memory location 1 which contains the branch instruction to the interrupt subroutine.

RT2: PC <- PC + 1 , IEN <- 0,
R <- 0, SC <- 0

At the beginning of the next instruction cycle (R = 0), fetching the branch instruction to the first instruction of the interrupt subroutine may begin.



PROBLEM 3.9(5-12)


The content of PC in the basic computer is 3AF (all numbers are in hexadecimal). The content of AC is 7EC3. The content of memory at address 3AF is 932E. The content of memory at address 32E is 09AC. The content of memory at address 9AC is 8B9F.

a) What is the instruction that will be fetched and executed next?

b) Show the binary operation that will be performed in the AC when the instruction is executed

c) Give the contents of registers PC, AR, DR, AC and IR in hexadecimal and the values of E, I and the sequence counter SC in binary at the end of the instruction cycle.

---------------------------------------------------------------------------

Solution:

a) (PC) = 3AF => next instruction that will be fetched is 932E that is indirect ADD instruction (from table 5-2). The address of the operand is at address 32E (instruction bits 0 - 11).

b) Address of the operand is 09AC at address 32E => operand is at address 09AC => operand is 8B9F

ADD command:

DR <- M[AR]
AC <- AC + DR ; operand is in DR
E <- Cout , SC <- 0 ; E = 1 if carry out

=> (AC) = (AC) + 8B9F = 7EC3 + 8B9F
=>

7EC3 = 0111 1110 1100 0011
+ 8B9F = 1000 1011 1001 1111
---------------------------------
1 0000 1010 0110 0010 = 0A62 (carry discarded)

c)

(PC) = 3B0 ; 3AF + 1
(AR) = 9AC ; Address of the last memory reference
(DR) = 8B9F ; 2'nd operand
(AC) = 0A62 ; The result of addition
(IR) = 932E ; Last instruction fetched = ADD
E = 1 ; we had carry out
(SC) = 0 ; Cleared at the end of ADD command
I = 1 ; indirect ADD




PROBLEM 3.10(5-22)

Derive the control gates for the write input of the memory in the basic computer.

See Table 5-6

---------------------------------------------------------------

Solution:

The logic gates associated with the write input of memory is derived by scanning Table 5-6 to find the statements that specify a write operation. The write operation is recognized from the symbol M[AR] <-.

WRITE = RT1 + D3T4 + D5T4 + D6T6
= RT1 + T4( D3 + D5 ) + D6T6

Posted Image



PROBLEM 3.11 (5-19)

The register transfer statements for a register R and the memory in a computer are as follows (the X's are control functions that occur at random):

X'3X1: R<-M[AR] Read memory word into R

X'1X2: R<-AC Transfer AC to R

X'1X3: M[AR]<-R Write R to memory

The memory has data inputs, data outputs, address inputs and control inputs to read and write as in Fig. 2-12. Draw the hardware implementation of R and the memory in block diagram form. Show how the control functions X1 through X3 select the load control input of R, the select inputs of multiplexers that you include in the diagram, and the read and write inputs of the memory.

See fig. 5-4

--------------------------------------------------------------
Solution:

Following statements change the contents of R (LD = 1):

x'3x1: R <- M[AR]
x'1x2: R <- AC
=> LD® = x1x'3 + x'1x2

Posted Image


Appendices

Figure 2-12

Posted Image

Figure 5-4
Posted Image

Figure 5-5
Posted Image

Figure 5-6
Posted Image


Figure 5-15

Posted Image

Figure 5-21
Posted Image
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#2 nonggiatu

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Gửi lúc 13 Apr 2008 - 04:34 AM

Tiếp phần appendices:

Figure 5-2
Posted Image

Figure 5-4
Posted Image

Figure 5-6
Posted Image

Chúc mọi người thi tốt. Posted Image
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#3 Guest_xuta_*

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Gửi lúc 13 Apr 2008 - 05:11 AM

Má ơi, nhìn đã chẳng muốn thi nữa rồi, híc híc ;-17 ;-17 ;-17

#4 langtu072

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Gửi lúc 13 Apr 2008 - 12:19 PM

nhin ma chan nan !





Van du khoi dau nan
Gian nan bat dau nan :((
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Người ta vá áo bằng kim
Tôi đây biết vá con tim bằng gì
Người ta hàn sắt bằng chì
Tui đây biết lấy thứ gì hàn tim




Nếu bạn là boy 100% còn chờ gì nữa !!! Click vô đây!!! fim Nóng hổi ....


#5 glassheart_124

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Gửi lúc 13 Apr 2008 - 04:27 PM

Hê, các bác có tài liệu môn này có thể post lên cho đàn em tham khảo được không?
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There Are Only 10 Types of People in the World: Those Who Understand Binary, and Those Who Don't.


4B6E6F776C6564676520497320506F7765720D0A
6275742049676E6F72616E636520497320426C69737300


#6 htcuong

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Gửi lúc 13 Apr 2008 - 09:53 PM

Đọc xong, ngất luôn :((
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Anh đâu chỉ đẹp trai !

#7 quydo

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Gửi lúc 14 Apr 2008 - 01:06 AM

Tiếng Việt còn không hiểu , nó lại đưa ra tiếng Anh :huh: :huh:
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#8 littlebook

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Gửi lúc 06 Jan 2009 - 12:10 PM

Cám ơn bạn nhiều. Mình sẽ cố gắng master nó.
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